1. Field of the Invention
The present invention relates to a frequency control apparatus and method which controls the frequency of an output signal thereof in synchronism with an externally input timing signal, and a storage medium storing a program for carrying out the method.
2. Prior Art
Conventionally, as a system for generating an output signal which is controlled in frequency in synchronism with an input signal applied thereto, a PLL (phase lock loop) is known. A typical PLL is essentially comprised of a phase comparator which compares the phase of an input signal and the phase of an output signal (regenerated clock signal), a loop filter which smoothes the output of the phase comparator, and a VCO (voltage controlled oscillator) which outputs the regenerated clock signal varying in frequency in response to the output of the loop filter. Further, in the case of regenerating a sampling clock having a frequency of 44.1 kHz in synchronism with an input signal having a frequency of 1 kHz, for example, a frequency divider, which reduces the frequency from 44.3 kHz to 1 kHz, is provided in a feedback loop to the phase comparator.
In a conventional PLL, all of the component elements are implemented by hardware, which leads to an increasing number of component elements. This is particularly true where many frequency dividing steps are used, resulting in a complicated construction. Moreover, in the conventional PLL, the input signal (data) entering response depends upon the time constant of the loop filter which cannot be easily changed. Consequently, if the input frequency differs greatly from the output frequency (e.g., input frequency &lt;&lt; output frequency), much time is necessary to enter the input signal. Further, in the conventional PLL, the component elements are selected for a particular input frequency/output frequency ratio. Therefore, the PLL cannot flexibly cope with input and output signals having a different frequency ratio.
Further, where the PLL is applied to an apparatus constructed such that a synchronizing signal as a timing signal is input from the personal computer or a like (hereinafter referred to as "PC") and an internal VCO is controlled in synchronism with the input synchronizing signal, if the synchronizing signal is not supplied with the power supply to PC off or a bus disconnected, the output frequency changes, causing a change in the operative state of the apparatus which operates in synchronism with the synchronizing signal. Moreover, when the power supply to PC is again turned on, there occurs a large difference between the input frequency and the output frequency. As mentioned above, in the conventional PLL, the input signal (data) entering response depends upon the time constant of the loop filter, and the time constant must be set to a rather large value so as to secure stability of the output frequency. Therefore, if there is a large difference between the input frequency and the output frequency, much time is needed to enter the input signal.